Video Processing IP Cores
Video and image processing algorithms often appear simple in concept, but applying mathematical transformations to multi-dimensional data sets and pixel arrays can be very challenging. Sophisticated buffer and pipeline management are often required to meet the throughput and latency performance objectives. Proper mathematical processing with sufficient intermediate bit depth and round-off handling is also critical to effective algorithm implementation.
Adaptive has implemented a wide variety of video processing functions, ranging from simple convolutions to sophisticated motion-adaptive de-interlacing functions. FPGA’s with embedded ARM cores provide an added dimension of adaptive control for advanced filtering techniques, using software to control the number-crunching logic, implemented within the FPGA core.
Adaptive understands FPGA-based image and video processing and is committed to delivering video processing IP cores that work for your product.
That’s what we do.
|FPGA IP Cores for Video Processing: